Why do AI chips manufactured in the United States need to be shipped to Taiwan for packaging?

Even though some high-performance AI wafers are already produced in the United States, due to the extreme concentration of capacity in the downstream manufacturing process, these semiconductor chips still need to be shipped across the ocean to Taiwan for advanced packaging. While this global division of labor is built on a mature technology ecosystem, it has also made “advanced packaging” the most fragile bottleneck in today’s AI supply chain. This excerpt is from CNBC’s documentary highlights.

The importance of chip packaging to AI

AI workloads require a large amount of data. Advanced packaging technologies (such as TSMC’s CoWoS or Intel’s EMIB) allow engineers to place high-bandwidth memory directly next to the computing chips within the same package. This creates a high-density, high-efficiency communication pathway, thereby avoiding data transmission bottlenecks.

Every AI chip, whether a GPU or a custom ASIC, ultimately must connect to a circuit board to operate in server racks. Advanced packaging technologies provide the necessary interconnects, typically involving tens of thousands of tiny wires to ensure these powerful chips can interact with the outside world. As the demand for these high-performance, complex configurations has grown faster than expected, the limited production capacity of advanced packaging technology has become the industry’s main constraint.

Advanced packaging is key to breaking through the memory wall

Conventional semiconductor manufacturing focuses on shrinking transistors, but as the physical limits of a single chip approach, Advanced Packaging becomes the key to breaking through the Memory Wall. By packaging multiple compute cores with High Bandwidth Memory, HBM (high-bandwidth memory) on the same substrate, a high-density and efficient communication pathway can be established, reducing data transmission latency. Current technology trends are shifting from 2.5D packaging toward 3D integration. The latter, through Die-to-Die stacking, significantly shortens the physical distance of signal transmission, enabling higher processing performance to be integrated within the limited space of data centers.

TSMC uses CoWoS advanced packaging to counter Intel’s EMIB

The two global foundry giants, TSMC and Intel, have developed different packaging architectures to meet AI demand. The CoWoS (Chip on Wafer on Substrate) technology used by TSMC uses a Silicon Interposer as an intermediary bridge, with extremely high-density wiring capability, and it has already evolved to specifications such as CoWoS-L that support larger memory stacking. Intel, on the other hand, developed embedded multi-die interconnect bridges (EMIB) technology. It does not use a full-size interposer layer; instead, it embeds localized silicon bridges into the substrate, aiming to improve material utilization and reduce costs. Both companies have also separately rolled out SOIC and Foveros Direct technologies, competing for leadership in the future 3D packaging market.

How can supply-chain geopolitical risk be breakeven?

At present, advanced packaging capacity is highly concentrated in Asia, especially Taiwan and South Korea. This geographic concentration has sparked discussions about geopolitics and logistics efficiency—for example, some chips manufactured in the United States still need to be shipped back to Taiwan for the final step of the process. This not only increases transportation time, but also involves potential regional and political risks. To address this situation, TSMC plans to build its first batch of advanced packaging factories in Arizona, and Intel is also gradually expanding its packaging operations within the United States. This reflects the semiconductor industry’s effort to diversify production nodes in order to strengthen supply-chain resilience.

The demand growth rate in the AI chip market has exceeded initial industry investment expectations, leading to a clear production capacity bottleneck in the packaging stage. Because leading companies such as NVIDIA have reserved most of TSMC’s CoWoS capacity, other competitors and developers of custom application-specific integrated circuits (ASICs) face challenges when trying to secure capacity. To ease the gap, major foundries and third-party specialized packaging and testing firms (OSAT) are rapidly increasing capital expenditures, attempting to meet the market’s demand for high-performance interconnect technology by expanding equipment and facilities.

Why do the U.S.-made AI chips in this article need to be shipped to Taiwan for packaging? First appeared on Liannews ABMedia.